FPGA Implementation of Novel Reconfigurable Pipelined Architectures for Low Complexity FIR Filters

The Finite Impulse Response (FIR) filters require two main factors known as low complexity and reconfigurability. The FIR filters are widely applied in multistandard wireless communications. The two significant factors that are achieved by proposing two main architectures namely Constant Shift Method (CSM) and Programmable Shift Method (PSM). The major factor of filter complexity is number of adders requires in the multiplier unit. The Common Sub-expression Elimination (CSE) algorithm used to efficiently reduce the number of adders in the multiplier unit and the introduction of the Canonical Signed Digit method (CSD) to implement the low complexity higher order FIR filter is proposed in this paper. The design results shows that the proposed architectures offers a good area and power reductions compared to all other existing methods to implement FIR filters. Here compared to CSM, PSM based CSD representation for filter coefficient offers a good area and power reduction with the cost of little high delay. To reduce the delay in PSM we are going to introduce a new architecture named as pipelined PSM architecture. The pipelined PSM architecture is efficiently reduce the area and power with less delay.